1/4 rev. b structure product name model name function silicon monolithic integrated circuits 1ch ldo regulator of mounting on micro side for 15v input bd9995nuv (1) input voltage: 15[v]max (2) output current: 0.6[a]max (3) low current consumption at the standby: 1[a] or lessstandard (4) built-in soft start function (5) built-in on/off function (6) built-in output voltage change ability function (7) over current protect ion?heating protection (8) vson008v2030 space saving achievement by package absolute maximum ratings (ta=25) item symbol limit unit supply voltage vcc -0.315.5 v power dissipation 12 pd 2.82 w operating temperature range topt -25+85 storage temperature range tstg -55+150 vout terminal maximum input voltage vinvout -0.3 vcc+ 0.3 v fb terminal maximum input voltage vinfb -0.3vcc+ 0.3 v en terminal maximum input voltage vinen -0.3vcc+ 0.3 v sel terminal maximum input voltage vinsel -0.3vcc+ 0.3 v junction temperature tjmax +150 1rohm 4 layer boar d76.2114.31.6[mm 3 ] the copper area on 2,3 layer 5655 mm 2 2power dissipation d epends on the mounted wiring pat tern. operating conditions (ta25) item symbol min. typ. max. unit supply voltage1sel=vcc 3 vcc1 8.7 12.0 15.0 v supply voltage2sel=open 3 vcc2 9.7 12.0 15.0 v supply voltage3sel=gnd 3 vcc3 10.7 12.0 15.0 v output currentvcc-vout=1.1v 3 iout - - 0.60 a 3 do not, however exceed pd.
2/4 rev. b electric characteristics unless otherwise specifi ed, vcc=12.0[v],ta=25[] parameter symbol limit unit condition min. typ. max. current consumption at stand by icc1 - 1.0 10.0 a vcc=12.0[v], sel=gnd current consumption when operating icc2 351 540 729 a vcc=12.0[v], sel=gnd no load output voltage1 vout1 7.84 8. 00 8.24 v vcc=12.0[v], sel=vcc output voltage2 vout2 8.82 9. 00 9.27 v vcc=12.0[v], sel=open output voltage3 vout3 9.80 10.00 10.30 v vcc=12.0[v], sel=gnd soft start time tsoft 0.45 0.85 1.25 s time of output voltage 85[%] en low input threshold vol tage vthenl 0 - 0.5 v en high input threshold voltage vthenh 2.4 - vcc v en input current iccen 53 75 97 ua en=3.0[v] ,vcc=12.0[v] minimum i/o voltage difference vio 0.8 v vout=10.0[v], output load =450[ma] package outline lot.no. ( unit:mm )
3/4 rev. b block diagram terminal no./terminal name terminal no terminal name 1 en 2 gnd 3 sel 4 fb 5 vout 6 vout 7 vcc 8 vcc
4/4 rev. b operation notes 1about ground potential ?.the ground line is where the lowest potential and transient v oltages are connected to the ic. moreover, all terminals except the terminal gnd must not become the voltage of gnd or less act ually including transients. 2about starting ?keep light load at vout output while start-up. 3about board pattern ? use separates ground lines for small control signals and high current outputs. because these high current outputs that flows to the wire impedance changes the gnd voltage for control signal. therefore each ground of ic must be connected at one point on the set circuit bo ard. as for gnd of external p arts, its similar to the above-mentioned. 4about peripheral circuit ? bypass capacitor between power supply and ground should be us e low esr ceramic capacitor and placed close to the ic pin as possible. the output condenser is necessary to be placed as near to the ic as possible with shortest distance. monitor the output voltage at both end of capacitor connected t o vout. 5about absolute maximum rating ? exceeding supply voltage and operating temp. over absolute ma ximum ratings may cause degradation of ic and even may destroy the ic. if special mode such that exceeding absolut e maximum ratings is expected, please have safe countermeasure such as adding poly switch and fuse to avoid fro m over stressing. 6about heat design ? do not exceed the power dissipa tion (pd) of the package speci fication rating under actual operation. 7about short between pins a nd the mis-installation ? while mounting ic on the printing board, check direction and position of the ic. if inadequat ely mounted, the ic may destroy . moreover this ic might be dest royed when dust short the termina ls between pins or pin and ground. 8about operation in strong electromagnetic field ? strong electromagnetic radiation can cause operation failures . 9about heat interception circuit (tsd) ? the heat interception circuit is built into this ic. when the junction temperature (tj) reaches 175, the output is switched to off. it is a circuit to aim to intercept ic from thermal rec kless driving to the last, and it aims at no protection and the guarantee of neither set nor ic. therefore, operate this circui t and use neither continuous use from now on nor operation. 10about over current protection circuit ? the over current protection ci rcuit is built into this ic. it operates by the effective one of the protection circuit contin uous for the destruction prevention due to broken accident, and avoi ds the load about this circuit about use to which the operation of this function is req uired because it is not the on e to the use when it is excessive ic destruction. 11about inspection by set substrate ? the stress might hang to ic by connecting the capacitor to th e terminal with low impedance. then, please discharge electricity in each and all process. moreover, in the inspectio n process, please turn off the power before mounting the ic, and turn on after mounting the ic . in addition, please take int o consideration the countermeasures for electrostatic damage, such as giving the earth in asse mbly process, transportation or preservation. 12about each input terminal ? this ic is a monolithic ic, and has p + isolation and p substrate for the element separation. therefor e, a parasitic pn junction is firmed in this p-layer and n-layer of each element. when the gnd voltage potential is greater than the voltage potential at terminals a or b, the pn junction operates as a parasitic di ode. in addition, the parasitic npn transistor is formed in sai d parasitic diode and the n layer of surrounding elements close t o said parasitic diode. these parasitic elements are formed in the ic because of the voltage re lation. the parasitic element o perating causes the wrong operation and destruction. therefore, please be careful so as not to operate the parasitic elements by impressing to input terminals lower voltage than gnd (p substrate). please do not apply the voltage to the input terminal when the power Csupply voltage is not impressed. moreover, please impress each input terminal lower than the power-supply voltage or equal to the specified range in the guaranteed voltage when the power- supply voltage is impressing.
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